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Generate hdl schematic with synplify pro3/15/2024 To create Digital Sine Top module, use steps for creating modules, Sub-c hapter 2.3.1 Creating a Module Using an Text Editor.Ĭntampl_value_g : integer := 255 - threshold value for counter, it's value should be equal to (2^depth)-1ĭepth_g : integer range 1 to 99 := 8 - the number of samples in one period of the signal div_factor_freqhigh_g: threshold value of frequency b.div_factor_freqhigh_g: threshold value of frequency a.width_g : the number of bits used to represent amplitude value.depth_g : the number of samples in one period of the signal.cnt_value_g : threshold value for counter, it's value should be equal to (2^depth)-1.sine_out : current amplitude value of the sine signal.sw0 : input signal from the on-board switch, used for changing output signal frequency.Drawing 6.2: Digital Sine Top detailed block diagram
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